Author: Fernandez Adiego, B.     [Fernández Adiego, B.]
Paper Title Page
WEPGF092 PLCverif: A Tool to Verify PLC Programs Based on Model Checking Techniques 1
  • D. Darvas, E. Blanco Vinuela, B. Fernández Adiego
    CERN, Geneva, Switzerland
  Model checking is a promising formal verification method to complement testing in order to improve the quality of PLC programs. However, its application typically needs deep expertise in formal methods. To overcome this problem, we introduce PLCverif, a tool that builds on our verification methodology and hides all the formal verification-related difficulties from the user, including model construction, model reduction and requirement formalisation. The goal of this tool is to make model checking accessible to the developers of the PLC programs. Currently, PLCverif supports the verification of PLC code written in ST (Structured Text), but it is open to other languages defined in IEC 61131-3. The tool can be easily extended by adding new model checkers.  
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