Author: Ha, K.
Paper Title Page
MOC3O05 NSLS-II Fast Orbit Feedback System 1
 
  • Y. Tian, W.X. Cheng, L.R. Dalesio, J.H. De Long, K. Ha, L. Yu
    BNL, Upton, Long Island, New York, USA
  • W.S. Levine
    UMD, College Park, Maryland, USA
 
  This paper presents the NSLS-II fast orbit feedback (FOFB) system, including the architecture, the algorithm and the commissioning results. A two-tier communication architecture is used to distribute the 10kHz beam position data (BPM) around the storage ring. The FOFB calculation is carried out in field programmable gate arrays (FPGA). An individual eigenmode compensation algorithm is applied to allow different eigenmodes to have different compensation parameters. The system is used as a regular tool to maintain the beam stability at NSLS-II.  
slides icon Slides MOC3O05 [10.087 MB]  
 
TUC3O05 NSLS-II ACTIVE INTERLOCK SYSTEM FOR FAST MACHINE PROTECTION 1
 
  • K. Ha, W.X. Cheng, L.R. Dalesio, J.H. De Long, Y. Hu, P. Ilinski, J. Mead, D. Padrazo, S. Seletskiy, O. Singh, R.M. Smith, Y. Tian
    BNL, Upton, Long Island, New York, USA
  • G. Shen
    FRIB, East Lansing, Michigan, USA
 
  Funding: Work supported by DOE contract No: DE-AC02-98CD10886
At National Synchrotron Light Source-II (NSLS-II), a field-programmable gate array (FPGA) based global active interlock system (AIS) has been commissioned and used for beam operations. The main propose of AIS is to protect insertion devices (ID) and vacuum chambers from the thermal damage of high density synchrotron radiation power. This report describes the status of AIS hardware, software architectures and operation experience.
 
slides icon Slides TUC3O05 [21.147 MB]  
 
WEPGF080 Encoder Interface for NSLS-II Beam Line Motion Scanning Applications 1
 
  • R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski
    BNL, Upton, Long Island, New York, USA
 
  The variety of motion control applications on existing and future NSLS-II beam lines demand custom control electronics developed to meet specific needs and ease integration to existing systems. Thus an encoder interface was designed for a number of detection techniques that require fly-scan applications. This design fits in a 2U chassis and can handle up to 4 incremental quadrature encoders with a digital RS-422A interface and output frequencies up to 10 MHz. The logic, based on Xilinx Virtex-6 FPGA, processes signals from an encoder, associates it with accelerator timestamp and sends the data to a server using TCP/IP stack, with the server side running an EPICS IOC. Several filtering and compression techniques are also applied. The device then re-translates the interface signals for the motion controller, allowing the device to be installed between encoder and motion controller with no interference to the system. The hardware leverages the NSLS-II BPM Digital Front End (DFE) board with Virtex-6 FPGA and periphery. The design harmoniously complements the family of NSLS-II equipment sharing same mechanical and electrical platform.  
poster icon Poster WEPGF080 [4.670 MB]