Author: Hill, J.O.
Paper Title Page
MOPGF161 LANSCE Control System Upgrade Status and Challenges 1
  • M. Pieck, D. Baros, E. Björklund, J.A. Faucett, J.G. Gioia, J.O. Hill, P.S. Marroquin, J.D. Paul, J.D. Sedillo, F.E. Shelley, H.A. Watkins
    LANL, Los Alamos, New Mexico, USA
  Funding: Work supported by Los Alamos National Laboratory for the U.S. Department of Energy under contract W-7405-ENG-36. LA-UR-15-27880
The Los Alamos Neutron Science Center (LANSCE) linear accelerator drives five user facilities: Isotope Production, Proton Radiography, Ultra-Cold Neutrons, Weapons Neutron Research, and Neutron Scattering. In 2011, we started an ambitious project to refurbish key elements of the LANSCE accelerator that have become obsolete or were near end-of-life. The control system went through an upgrade process that affected different areas of LANSCE. Many improvements have been made but funding challenges and LANSCE operational commitments have delayed project deliverables. In this paper, we will discuss our upgrade choices, what we have accomplished so far, what we have learned about upgrading the existing control system and what challenges we still face.
poster icon Poster MOPGF161 [1.069 MB]  
THHA2O02 The LASNCE FPGA Embedded Signal Processing Framework 1
  • J.O. Hill
    LANL, Los Alamos, New Mexico, USA
  Funding: Work supported by US Department of Energy under contract DE-AC52-06NA25396.
During the replacement of some LANSCE LINAC instrumentation systems a common architecture for timing system synchronized embedded signal processing systems was developed. The design follows trends of increasing levels of electronics system integration; a single commercial-off-the-shelf (COTS) board assumes the roles of analog-to-digital conversion and advanced signal processing while also providing the LAN attached EPICS IOC functionality. These systems are based on agile FPGA-based COTS VITA VPX boards with an VITA FMC mezzanine site. The signal processing is primarily developed at a high level specifying numeric algorithms in software source code to be integrated together with COTS signal processing intellectual property components for synthesis of hardware implementations. This paper will discuss the requirements, the decision point selecting the VPX together with the FMC industry standards, the benefits along with costs of system integrating multi-vendor COTS components, the design of some of the signal processing algorithms, and the benefits along with costs of embedding the EPICS IOC within an FPGA.
slides icon Slides THHA2O02 [2.108 MB]