Author: Straumann, T.
Paper Title Page
MOPGF002 Magnet Corrector Power Supply Controller for LCLS-I 1
 
  • S. Babel, B. Lam, K. Luchini, J.J. Olsen, T. Straumann, E. Williams, C. Yee
    SLAC, Menlo Park, California, USA
 
  The MCOR-12[Magnet Corrector] is a 16-channel modular architecture, precision magnet driver, capable of providing bipolar output currents in the range from 12A to +12A. A single, unregulated bulk power supply provides the main DC power for the entire crate. Currently the MCORs have a 1000ppm regulation on the B-field. The MCOR controller card upgrades, existing LCLS-I and future LCLS-II needed, controls for Magnet Corrector Power Supplies. The project shifts the existing functionality of the VME based DAC and SAM and an Allen Bradley PLC into a new slot-0 card residing in the MCOR chassis. Elimination of the VME crate and the PLC will free up rack space to be used in future. The new interface card has a long term stability of 100 ppm and monitors ground fault currents and various other interlocks for the MCOR power supplies. The controller can interface to EPICS Channel Access and Fast Feedback system at SLAC using two Gigabit Ethernet ports and has an FPGA based EVR for getting 'time stamps' from the Event Generator system at SLAC. The EPICS control system along with embedded diagnostic features will allow for enhanced remote control and monitoring of the power supplies.
*S. Babel, S. Cohen, "Digital Control Interface for Bipolar Corrector Power, BiRa Systems, Albuquerque **G.E. Leyh, "A Multi-Channel Corrector Magnet Controller"
 
poster icon Poster MOPGF002 [1.646 MB]  
 
MOPGF038 Design and Commissioning Results of MicroTCA Stripline BPM System 1
 
  • S. L. Hoobler, R.S. Larsen, H. Loos, J.J. Olsen, S.R. Smith, T. Straumann, C. Xu, A. Young
    SLAC, Menlo Park, California, USA
 
  The Linac Coherent Light Source (LCLS) is a free electron laser (FEL) facility operating at the SLAC National Accelerator Laboratory (SLAC). A stripline beam position monitor (BPM) system was developed at SLAC [1] to meet the performance requirements necessary to provide high-quality stable beams for LCLS. This design has been modified to achieve improved position resolution in a more compact form factor. Prototype installations of this system have been operating in the LCLS LINAC and tested at the Pohang Accelerator Laboratory (PAL). Production systems are deployed at the new PAL XFEL facility and at the SPEAR storage ring at the Stanford Synchrotron Radiation Lightsource at SLAC. This paper presents the design and commissioning results of this system.  
poster icon Poster MOPGF038 [0.809 MB]  
 
WEPGF122 Real-Time Performance Improvements and Consideration of Parallel Processing for Beam Synchronous Acquisition (BSA) 1
 
  • K.H. Kim, S. Allison, T. Straumann, E. Williams
    SLAC, Menlo Park, California, USA
 
  Funding: Work supported by the the U.S. Department of Energy, Office of Science under Contract DE-AC02-76SF00515 for LCLS I and LCLS II.
Beam Synchronous Acquisition (BSA) provides a common infrastructure for aligning data to each individual beam pulse, as required by the Linac Coherent Light Source (LCLS). BSA allows 20 independent acquisitions simultaneously for the entire LCLS facility and is used extensively for beam physics, machine diagnostics and operation. BSA is designed as part of LCLS timing system and is currently an EPICS record based implementation, allowing timing receiver EPICS applications to easily add BSA functionality to their own record processing. However, the non-real-time performance of EPICS record processing and the increasing number of BSA devices has brought real-time performance issues. The major reason for the performance problem is likely due to the lack of separation between time-critical BSA upstream processing and non-critical downstream processing. BSA is being improved with thread level programming, breaking the global lock in each BSA device, adding a queue between upstream and downstream processing, and moving out the non-critical downstream to a lower priority worker thread. The use of multiple worker threads for parallel processing in SMP systems is also being investigated.
 
poster icon Poster WEPGF122 [1.665 MB]