Author: Terpstra, W.W.
Paper Title Page
MOPGF147 Realization of a Concept for Scheduling Parallel Beams in the Settings Management System for FAIR 1
 
  • H.C. Hüther, J. Fitzek, R. Müller, A. Schaller, W.W. Terpstra
    GSI, Darmstadt, Germany
 
  Approaching the commissioning of CRYRING, the first accelerator to be operated using the new control system for FAIR (Facility for Antiproton and Ion Research), the new settings management system will also be deployed in a production environment for the first time. A major development effort is ongoing to realize requirements necessary to support accelerator operations at FAIR. The focus is on the pattern concept which allows controlling the whole facility with its different parallel beams in an integrative way. Being able to utilize central parts of the new control system already at CRYRING, before the first FAIR accelerators are commissioned, facilitates an early proof of concept and testing possibilities. Concurrently, refactorings and enhancements of the commonly used LSA (LHC Software Architecture) framework take place. At CERN, the interface to devices has been redesigned to enhance maintainability and diagnostics capabilities. At GSI, support for polynomials as a native datatype has been implemented, which will be used to represent accelerator settings as well as calibration curves. Besides functional improvements, quality assurance measures are being taken to increase code quality in prospect of productive use.  
poster icon Poster MOPGF147 [1.516 MB]  
 
WEPGF119 Bunch to Bucket Transfer System for FAIR 1
 
  • J.N. Bai
    IAP, Frankfurt am Main, Germany
  • R. Bär, D. Beck, O.K. Kester, D. Ondreka, C. Prados, W.W. Terpstra
    GSI, Darmstadt, Germany
  • T. Ferrand
    TEMF, TU Darmstadt, Darmstadt, Germany
 
  For the FAIR accelerator complex, synchronization of the bunch to bucket (B2B) transfer will be realized by the General Machine Timing system and the Low-Level RF system. Based on these two systems, both synchronization methods, the phase shift and the frequency beating method, are available for the B2B transfer system for FAIR. This system is capable to realize the B2B transfer within 10ms and the precision better than 1 degree for ions over the whole range of stable isotopes. At first, this system will be used for the transfer from the SIS18 to the SIS100. It will then be extended to all transfers at the FAIR accelerator facility. This paper introduces the synchronization methods and concentrates on the standard procedures and the functional blocks of the B2B transfer system.  
poster icon Poster WEPGF119 [1.489 MB]  
 
THHA2O03 Message Signalled Interrupts in Mixed-Master Control 1
 
  • W.W. Terpstra, M. Kreider
    GSI, Darmstadt, Germany
 
  Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.  
slides icon Slides THHA2O03 [0.758 MB]