Hardware Technology
Paper Title Page
WEM307 Custom Hardware Platform Based on Intel Edison Module 1
 
  • D. Pedretti, D. Bortolato, F. Gelain, M.G. Giacchini, D. Marcato, M. Montis, S. Pavinato, J.A. Vásquez
    INFN/LNL, Legnaro (PD), Italy
  • M.A. Bellato, R. Isocrate
    INFN- Sez. di Padova, Padova, Italy
 
  The Computer-on-Module approach makes cutting edge technology easily accessible and lowers the entry barriers to anyone prototyping and developing embedded systems. Furthermore, it is possible to add all the system specific functionalities to the generic PC functions which are readily available in an off-the-shelf core module reducing the time to market and enhancing the creativity of system engineers. The purpose of this paper is to show a custom hardware platform based on the tiny and low power Intel Edison Compute Module, which uses a 22nm Intel processing core and contains connectivity elements to ensure device-to-device and device-to-cloud connectivity. The Intel Edison carrier board designed is expected to act as a local intelligent node, a readily available custom EPICS*,** IOC for extending the control reach to small appliances in the context of the SPES project. The board acts as an Ethernet to RS232/RS422 interface translator with Power-Over-Ethernet supply and network booting as key features of this platform. The x86 architecture of the Edison makes standard Linux software deployment straightforward. Currently the board is in prototyping stage.
*http://www.aps.anl.gov/epics**http://www.lnl.infn.it/~epics
 
slides icon Slides WEM307 [1.052 MB]  
poster icon Poster WEM307 [2.495 MB]  
 
WEPGF074 FPGA Firmware Framework for MTCA.4 AMC Modules 1
 
  • Ł. Butkowski, T. Kozak, B.Y. Yang
    DESY, Hamburg, Germany
  • P. Prędki
    TUL-DMCS, Łódź, Poland
  • R. Rybaniec
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
 
  Many of the modules in specific hardware architectures use the same or similar communication interfaces and IO connectors. MicroTCA (MTCA.4) is one example of such a case. All boards: communicate with the central processing unit (CPU) over PCI Express (PCIe), send data to each other using Multi-Gigabit Transceivers (MGT), use the same backplane resources and have the same Zone3 IO or FPGA mezzanine card (FMC) connectors. All those interfaces are connected and implemented in Field Programmable Gate Array (FPGA) chips. It makes possible to separate the interface logic from the application logic. This structure allows to reuse already done firmware for one application and to create new application on the same module. Also, already developed code can be reused in new boards as a library. Proper structure allows the code to be reused and makes it easy to create new firmware. This paper will present structures of firmware framework and scripting ideas to speed up firmware development for MTCA.4 architecture. European XFEL control systems firmware, which uses the described framework, will be presented as example.  
poster icon Poster WEPGF074 [0.702 MB]  
 
WEPGF080 Encoder Interface for NSLS-II Beam Line Motion Scanning Applications 1
 
  • R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski
    BNL, Upton, Long Island, New York, USA
 
  The variety of motion control applications on existing and future NSLS-II beam lines demand custom control electronics developed to meet specific needs and ease integration to existing systems. Thus an encoder interface was designed for a number of detection techniques that require fly-scan applications. This design fits in a 2U chassis and can handle up to 4 incremental quadrature encoders with a digital RS-422A interface and output frequencies up to 10 MHz. The logic, based on Xilinx Virtex-6 FPGA, processes signals from an encoder, associates it with accelerator timestamp and sends the data to a server using TCP/IP stack, with the server side running an EPICS IOC. Several filtering and compression techniques are also applied. The device then re-translates the interface signals for the motion controller, allowing the device to be installed between encoder and motion controller with no interference to the system. The hardware leverages the NSLS-II BPM Digital Front End (DFE) board with Virtex-6 FPGA and periphery. The design harmoniously complements the family of NSLS-II equipment sharing same mechanical and electrical platform.  
poster icon Poster WEPGF080 [4.670 MB]  
 
WEPGF081 Em# Platform: Towards a Hardware Interface Standardization Scheme 1
 
  • O. Matilla, J.A. Avila-Abellan, M. Broseta, G. Cuní, D. Fernandez-Carreiras, A. Ruz, J. Salabert, X. Serra-Gallifa
    ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
 
  Low current measurements developments have been pointed out as strategic for ALBA synchrotron. From the first day of operation of the seven Beamlines currently in operation ALBA Em electrometer this has been successfully used. Today, the two new beamlines of Phase 2 that are being constructed and the new end stations have required specification changes in terms of increased accuracy, capability of synchronization, timestamping, management of large buffers and high performance closed-loop implementation. The scheme of full custom hardware design has been abandoned. ALBA Em# project approach has been based in the selection of industry standard interfaces: FMC boards design for custom needs, FMC carrier over PCIe using SPEC board from CERN under OHWR license, and Single Board Computer using PCIe to implement interfaces with the control system. This Paper describes the new design of the Electrometers at Alba, suited for the newer requirements, more flexible, performing and maintainable, which profits from the know-how acquired with previous versions and suits the new data acquisition paradigm emerged with the standardization of quick continuous scans and data acquisition.  
poster icon Poster WEPGF081 [0.230 MB]  
 
WEPGF083 Single Neutron Counting Using CCD and CMOS Cameras 1
 
  • P. Mutti, M. Plaz, E. Ruiz-Martinez, P. Van Esch
    ILL, Grenoble, France
  • M. Crisanti
    Università degli di Perugia, Perugia, Italy
 
  Neutron detection traditionally takes place with detectors based upon particle detection technologies like gas or scintillation detections. These detectors have a high dynamic range, and are very performing at low counting rates and fast timing (time of flight) applications. At high counting rates however, continuous imaging detectors such as CCD or CMOS camera's optically linked to scintillators, can have very good performances concerning linearity and spatial resolution but the dynamic range of these systems is limited by noise and gamma background. We explore a technique that allows us to use imaging detectors as counting detectors at lower counting rates, and transits smoothly to continuous imaging at higher rates. Neutron detection involves reactions releasing energies of the order of the MeV, while X-ray detection releases energies of the order of the photon energy, (10 KeV range). This 100-fold higher energy allows the individual neutron detection light signal to be significantly above the noise level, as such allowing for discrimination and individual counting. The theory is next confronted with experimental measurements on CCD and CMOS type commercial cameras.  
poster icon Poster WEPGF083 [7.975 MB]  
 
WEPGF084 New Digitisers for Position Sensitive 3He Proportional Counters 1
 
  • P. Mutti, M. Plaz, E. Ruiz-Martinez, P. Van Esch
    ILL, Grenoble, France
 
  3He gas-filled detectors are a classical choice for the detection of thermal and cold neutrons. The incident neutrons are captured by the 3He producing a tritium and an hydrogen which are sharing the 765 keV of energy generated in the reaction. The classical geometry of a charge-division neutron detector consists of a cylindrical volume housing a resistive anode. Electrical signals are extracted at both ends of the tube and the information about the interaction point along the tube can be derived from the ratio of the collected charged at both ends. The classical analog approach for the charge readout consists of a shaping amplifier coupled with a peak sensing ADC. The development of a new digital front-end electronics based on 64 channels, 62.5 Msample/s and 12 bit digitisers, is reported on. Excellent results have been obtained in terms of position resolution and signal to noise ratio when adopting a continuous digital filtering and gaussian shaping.  
poster icon Poster WEPGF084 [8.285 MB]  
 
WEPGF085 The Construction of the SuperKEKB Magnet Control System 1
 
  • T.T. Nakamura, A. Akiyama, M. Iwasaki, H. Kaji, J.-I. Odagiri, S. Sasaki
    KEK, Ibaraki, Japan
  • T. Aoyama, T. Nakamura, K. Yoshii
    Mitsubishi Electric System & Service Co., Ltd, Tsukuba, Japan
  • N. Yoshifuji
    EJIT, Hitachi, Ibaraki, Japan
 
  There were more than 2500 magnet power supplies for KEKB storage rings and injection beam transport lines. For the remote control of such a large number of power supplies, the Power Supply Interface Controller Module (PSICM), which is plugged into each power supply, was developed. It has a microprocessor, ARCNET interface, trigger signal input interface, and parallel interface to the power supply. The PSICM is not only an interface card but also controls synchronous operation of the multiple power supplies with an arbitrary tracking curve. For SuperKEKB we have developed the upgraded version of the PSICM. It has the fully backward compatible interface to the power supply. The enhanced features includes high speed ARCNET communication and redundant trigger signals. Towards the phase 1 commissioning of SuperKEKB, the construction of the magnet control system is ongoing. First mass production of 1000 PSICMs has been completed and their installation is in progress. The construction status of the magnet control system is presented in this paper.  
poster icon Poster WEPGF085 [2.287 MB]  
 
WEPGF089 CERN Open Hardware Experience: Upgrading the Diamond Fast Archiver 1
 
  • I.S. Uzun, M.G. Abbott
    DLS, Oxfordshire, United Kingdom
 
  Diamond Light Source developed and integrated the Fast Archiver into its Fast Orbit Feedback communication network in 2009. It enabled synchronous capture and archive of the entire position data in real-time from all Electron Beam Position Monitors (BPMs) and X-RAY BPMs . The FA Archiver solution has also been adopted by SOLEIL and ESRF. However, the obsolescence of the existing PCI Express based FPGA board from Xilinx and continuing interest from community forced us to look for a new hardware platform while keeping the back compatibility with the existing Linux kernel driver and application software. This paper reports our experience with using the PCIe SPEC board from CERN Open Hardware initiative as the new FA Archiver platform. Implementation of the SPEC-based FA Archiver has been successfully completed and recently deployed at ALBA in Spain.  
poster icon Poster WEPGF089 [0.576 MB]  
 
WEPGF090 Design of EPICS IOC Based on RAIN1000Z1 ZYNQ Module 1
 
  • T. Xue, G.H. Gong, H. Li, J.M. Li
    Tsinghua University, Beijing, People's Republic of China
 
  ZYNQ is the new architecture of FPGA with dual high performance ARM Cortex-A9 processors from Xilinx. A new module with Giga Bit Ethernet interface based on the ZYNQ XC7Z010 is development for the High Purity Germanium Detectors' data acquisition in the CJPL (China JingPing under-ground Lab) experiment, which is named as RAIN1000Z1. Base on the nice RAIN1000Z1 hardware platform, EPICS is porting on the ARM Cortex-A9 processor with embedded Linux and an Input Output Controller is implemented on the RAIN1000Z1 module. Due to the combination of processor and logic and new silicon technology of ZYNQ, embedded Linux with TCP/IP sockets and real time high throughput logic based on VHDL are running in a single chip with small module hardware size, lower power and higher performance. This paper will introduce how to porting the EPICS IOC application on the ZYNQ based on embedded Linux and give a demo of IO control and RS232 communication.  
poster icon Poster WEPGF090 [1.777 MB]  
 
THHA2I01 Developing Distributed Hard-Real Time Software Systems Using FPGAs and Soft Cores 1
 
  • T. Włostowski, J. Serrano
    CERN, Geneva, Switzerland
  • F. Vaga
    University of Pavia, Pavia, Italy
 
  Hard real-time systems guarantee by design that no deadline is ever missed. In a distributed environment such as particle accelerators, there is often the extra requirement of having diverse real-time systems synchronize to each other. Implementations on top of general-purpose multi-tasking operating systems such as Linux generally suffer from lack of full control of the platform. On the other hand, solutions based on logic inside FPGAs can result in long development cycles. A mid-way approach is presented which allows fast software development yet guarantees full control of the timing of the execution. The solution involves using soft cores inside FPGAs, running single tasks without interrupts and without an operating system underneath. Two CERN developments are presented, both based on a unique free and open source HDL core comprising a parameterizable number of CPUs, logic to synchronize them and message queues to communicate with the local host and with remote systems. This development environment is being offered as a service to fill the gap between Linux-based solutions and full-hardware implementations.  
slides icon Slides THHA2I01 [2.525 MB]  
 
THHA2O02 The LASNCE FPGA Embedded Signal Processing Framework 1
 
  • J.O. Hill
    LANL, Los Alamos, New Mexico, USA
 
  Funding: Work supported by US Department of Energy under contract DE-AC52-06NA25396.
During the replacement of some LANSCE LINAC instrumentation systems a common architecture for timing system synchronized embedded signal processing systems was developed. The design follows trends of increasing levels of electronics system integration; a single commercial-off-the-shelf (COTS) board assumes the roles of analog-to-digital conversion and advanced signal processing while also providing the LAN attached EPICS IOC functionality. These systems are based on agile FPGA-based COTS VITA VPX boards with an VITA FMC mezzanine site. The signal processing is primarily developed at a high level specifying numeric algorithms in software source code to be integrated together with COTS signal processing intellectual property components for synthesis of hardware implementations. This paper will discuss the requirements, the decision point selecting the VPX together with the FMC industry standards, the benefits along with costs of system integrating multi-vendor COTS components, the design of some of the signal processing algorithms, and the benefits along with costs of embedding the EPICS IOC within an FPGA.
 
slides icon Slides THHA2O02 [2.108 MB]  
 
THHA2O03 Message Signalled Interrupts in Mixed-Master Control 1
 
  • W.W. Terpstra, M. Kreider
    GSI, Darmstadt, Germany
 
  Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.  
slides icon Slides THHA2O03 [0.758 MB]  
 
THHB2O01 Preliminary Design of a Real-Time Hardware Architecture for eRHIC 1
 
  • R.J. Michnoff, P. Cerniglia, M.R. Costanzo, R.L. Hulsart, J.P. Jamilkowski, W.E. Pekrul, Z. Sorrell, C. Theisen
    BNL, Upton, Long Island, New York, USA
 
  Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-SC0012704 with the U.S. Department of Energy.
The 3.8 km circumference Relativistic Heavy Ion Collider (RHIC) at BNL has been in operation since 2000. An electron-ion collider (eRHIC), which is in the design phase, plans to use one of the existing ion rings and new electron rings constructed in the existing tunnel to provide collisions of up to 21.2 GeV electrons with up to 100 GeV gold ions, 250 GeV polarized protons, as well as other species. Many new real-time systems will be required to satisfy the needs of eRHIC, including over 2000 beam position monitors, 1000 beam loss monitors, 18 current monitors, feedback systems, controls for about 10,000 power supplies, machine protection system, new beam timing systems, and more. The selected architecture must be flexible, expandable, cost-effective, reliable, and easy to maintain. Interface with existing and new accelerator timing systems is required, and compatibility with existing infrastructure and equipment must be maintained. Embedded modules based on the Xilinx Zynq gate array, with direct Ethernet connection and on-board Linux, housed in multi-slot chassis (VME, VPX, TCA, etc.) is under consideration. Preliminary design concepts for the architecture will be presented.
 
slides icon Slides THHB2O01 [7.735 MB]  
 
THHB2O02 A Modular Approach to Acquisition Systems for Future CERN Beam Instrumentation Developments 1
 
  • A. Boccardi, M. Barros Marin, T.E. Levens, W. Viganò, C. Zamantzas
    CERN, Geneva, Switzerland
 
  This paper will present the new modular architecture adopted as a baseline by the CERN Beam Instrumentation Group for its future acquisition system developments. The main blocks of this architecture are: radiation tolerant digital front-ends; a latency deterministic multi gigabit optical link; a high pin count FMC carrier used as a VME-based back-end for data concentration and processing. Details will be given on the design criteria for each of these modules as well as examples of their use in systems currently being developed at CERN.  
slides icon Slides THHB2O02 [2.051 MB]  
 
THHB2O03 The Global Trigger with Online Vertex Fitting for Low Energy Neutrino Research 1
 
  • G.H. Gong, H. Li, T. Xue
    Tsinghua University, Beijing, People's Republic of China
  • H. Gong
    TUB, Beijing, People's Republic of China
 
  Neutrino research is of great importance for particle physics, astrophysics and cosmology, the JUNO (Jiangmen Underground Neutrino Observatory) is a multi-purpose neutrino experiment for neutrino mass ordering determination and precision measurement of neutrino mixing parameters. A brand new global trigger scheme with online vertex fitting has been proposed, aiming at the ultra-low anti-neutrino energy threshold as down to 0.1MeV which is essential for the study of solar neutrino and elastic scattering of neutrinos on supernova burst. With this scheme, the TOF (time of flight) difference of photons fly through the liquid media from the interaction point to the surface of central detector can be corrected online with real time, the width of trigger window to cover the whole period of a specific neutrino generated photons can be significantly reduced which lessen the integrated dark noise introduced from the large amount of PMT devices hence a lower energy threshold can be achieved. The scheme is compatible, flexible and easy to implement, it can effectively extend the physics potential of the JUNO for low energy neutrino research topics.  
slides icon Slides THHB2O03 [4.252 MB]