Keyword: FPGA
Paper Title Other Keywords Page
MOC3O05 NSLS-II Fast Orbit Feedback System feedback, injection, operation, storage-ring 1
  • Y. Tian, W.X. Cheng, L.R. Dalesio, J.H. De Long, K. Ha, L. Yu
    BNL, Upton, Long Island, New York, USA
  • W.S. Levine
    UMD, College Park, Maryland, USA
  This paper presents the NSLS-II fast orbit feedback (FOFB) system, including the architecture, the algorithm and the commissioning results. A two-tier communication architecture is used to distribute the 10kHz beam position data (BPM) around the storage ring. The FOFB calculation is carried out in field programmable gate arrays (FPGA). An individual eigenmode compensation algorithm is applied to allow different eigenmodes to have different compensation parameters. The system is used as a regular tool to maintain the beam stability at NSLS-II.  
slides icon Slides MOC3O05 [10.087 MB]  
MOM308 XFEL Machine Protection System (MPS) Based on uTCA linac, kicker, operation, undulator 1
  • S. Karstensen, M.E. Castro Carballo, J.M. Jäger, M. Staack
    DESY, Hamburg, Germany
  For the operation of a machine like the 3 km long linear accelerator XFEL at DESY Hamburg, a safety system keeping the beam from damaging components is obligatory. This machine protection system (MPS) must detect failures of the RF system, magnets, and other critical components in various sections of the XFEL as well as monitor beam and dark current losses, and react in an appropriate way by limiting average beam power, dumping parts of the macro-pulse, or, in the worst case, shutting down the whole accelerator. It has to consider the influence of various machine modes selected by the timing system. The MPS provides the operators with clear indications of error sources, and offers the possibility to mask any input channel to facilitate the operation of the machine. In addition, redundant installation of critical MPS components will help to avoid unnecessary downtime. This paper summarizes the requirements on the machine protection system and includes plans for its architecture and for needed hardware components. It will show up the clear way of configuring this system - not programming. Also a look into the financial aspects (manpower / maintenance / integration) will be presented.  
slides icon Slides MOM308 [1.487 MB]  
MOPGF057 Quick Experiment Automation Made Possible Using FPGA in LNLS software, experiment, Linux, EPICS 1
  • M.P. Donadio, J.R. Piton, H.D. de Almeida
    LNLS, Campinas, Brazil
  Beamlines in LNLS are being modernized to use the synchrotron light as efficiently as possible. As the photon flux increases, experiment speed constraints become more visible to the user. Experiment control has been done by ordinary computers, under a conventional operating system, running high-level software written in most common programming languages. This architecture presents some time issues as computer is subject to interruptions from input devices like mouse, keyboard or network. The programs quickly became the bottleneck of the experiment. To improve experiment control and automation speed, we transferred software algorithms to a FPGA device. FPGAs are semiconductor devices based around a matrix of logic blocks reconfigurable by software. The results of using a NI Compact RIO device with FPGA programmed through LabVIEW for adopting this technology and future improvements are briefly shown in this paper.  
poster icon Poster MOPGF057 [5.360 MB]  
MOPGF091 White-Rabbit Based Revolution Frequency Program for the Longitudinal Beam Control of the CERN PS controls, proton, ion, injection 1
  • D. Perrelet, Y. Brischetto, H. Damerau, A.V. Villanueva
    CERN, Geneva, Switzerland
  • D. Oberson
    HEIA-FR, Fribourg, Switzerland
  • M.V. Sundal
    IST, Lisboa, Portugal
  The measured bending field of the CERN Proton Synchrotron (PS) is received in real-time by the longitudinal beam control system and converted into the revolution frequency used as set-point for beam phase and radial loops. With the renovation of the bending field measurement system the transmission technique is changed from a differential sequence of pulses, the so-called B-train, to a stream of Ethernet frames based on the White Rabbit protocol. The packets contain field, its derivative and auxiliary information. A new frequency program for the conversion of the bending field into the revolution frequency, depending also on parameters like radius of the accelerator and the particle type, has been developed. Instead of storing large conversion tables from field to frequency for fixed parameters, the frequencies are directly calculated in programmable logic (FPGA). In order to reduce development time and keep flexibility, the conversion is processed in real-time in the FPGA using Xilinx floating-point primitives mapped by a higher level tool Simulink System Generator. Commissioning with beam of the new frequency program in the PS is progressing.
Authors: D. Perrelet, Y. Brischetto, H. Damerau, D. Oberson, M. Sundal, A. Villanueva
poster icon Poster MOPGF091 [0.991 MB]  
MOPGF097 Architecture of Transverse Multi-Bunch Feedback Processor at Diamond feedback, controls, EPICS, experiment 1
  • M.G. Abbott, G. Rehm, I.S. Uzun
    DLS, Oxfordshire, United Kingdom
  We describe the detailed internal architecture of the Transverse Multi-Bunch Feedback processor used at Diamond for control of multi-bunch instabilities and measurement of betatron tunes. Bunch by bunch selectable control over feedback filters, gain and excitation allows fine control over feedback, allowing for example the single bunch in a hybrid or camshaft fill pattern to be controlled independently from the bunch train. It is also possible to excite all bunches at a single frequency while simultaneously sweeping the excitation for tune measurement of a few selected bunches. The single frequency excitation has been used for continuous measurement of the beta-function. A simple programmable event sequencer provides support for up to 7 steps of programmable sweeps and changes to feedback and excitation, allowing a variety of complex and precisely timed beam characterisation experiments including grow-damp measurements in unstable conditions and programmed bunch cleaning. Finally input and output compensation filters allow for correction of front end and amplifier phasing at higher frequencies.  
poster icon Poster MOPGF097 [0.247 MB]  
MOPGF098 PandA Motion Project - A Collaboration Between SOLEIL and Diamond to Upgrade Their 'Position and Acquisition' Processing Platform. interface, hardware, controls, software 1
  • I.S. Uzun, T.M. Cobb, A.M. Cousins, M.T. Heron
    DLS, Oxfordshire, United Kingdom
  • Y.-M. Abiven, J. Bisou, P. Monteiro, G. Renaud
    SOLEIL, Gif-sur-Yvette, France
  Synchrotron SOLEIL and Diamond Light Source are two third generation light sources located respectively in France and the UK. In the past 5 years, both facilities separately developed their own platform permitting encoder processing to synchronize motion systems and acquisition during experiments, SPIETBOX by SOLEIL and Zebra by Diamond. New operational requirements for simultaneous and multi-technique scanning, and support of multiple encoder standards have been identified by both institutes. In order to address these a collaborative project has been initiated between SOLEIL and Diamond to realize a new 'Position and Acquisition' processing platform, called PandA. The PandA project addresses current systems' limitations in term of obsolescence and need for more processing power. Its design is going to be a 1U standalone system powered by a Xilinx Zynq SoC to implement a configurable set of logic functionalities. It will provide a flexible and open solution to interface different third party hardware (detectors and motion Controllers). This paper details the organization of this collaboration, sharing technical leadership between both institutes and the status of the project.  
poster icon Poster MOPGF098 [1.953 MB]  
MOPGF122 A Fast Interlock Detection System for High-Power Switch Protection kicker, interface, Ethernet, operation 1
  • P. Van Trappen, E. Carlier, S. Uyttenhove
    CERN, Geneva, Switzerland
  Fast pulsed kicker magnet systems are powered by high-voltage and high-current pulse generators with adjustable pulse length and amplitude. To deliver this power, fast high-voltage switches such as thyratrons and GTOs are used to control the fast discharge of pre-stored energy. To protect the machine and the generator itself against internal failures of these switches several types of fast interlocks systems are used at TE-ABT (CERN Technology department, Accelerator Beam Transfer). To get rid of this heterogeneous situation, a modular digital Fast Interlock Detection System (FIDS) has been developed in order to replace the existing fast interlocks systems. In addition to the existing functionality, the FIDS system will offer new functionalities such as extended flexibility, improved modularity, increased surveillance and diagnostics, contemporary communication protocols and automated card parametrization. A Xilinx Zynq®-7000 SoC has been selected for implementation of the required functionalities so that the FPGA (Field Programmable Gate Array) can hold the fast detection and interlocking logic while the ARM® processors allow for a flexible integration in CERN's Front-End Software Architecture (FESA) framework, advanced diagnostics and automated self-parametrization.  
poster icon Poster MOPGF122 [0.861 MB]  
MOPGF132 Building an Interlock: Comparison of Technologies for Constructing Safety Interlocks PLC, controls, interlocks, hardware 1
  • T. Hakulinen, F. Havart, P. Ninin, F. Valentini
    CERN, Geneva, Switzerland
  Interlocks are an important feature of both personnel and machine protection systems for mitigating risks inherent in operation of dangerous equipment. The purpose of an interlock is to secure specific equipment or entire systems under well defined conditions in order to prevent accidents from happening. Depending on specific requirements for the level of reliability, availability, speed, and cost of the interlock, various technologies are available. Different approaches are discussed, in particular in the context of personnel safety systems, which have been built or tested at CERN during the last few years. Technologies discussed include examples of programmable devices, PLCs and FPGAs, as well as wired logic based on relays and special logic cards.  
poster icon Poster MOPGF132 [1.249 MB]  
MOPGF134 Design of Fast Machine Protection System for the C-ADS Injection I controls, interface, network, timing 1
  • F. Liu, J. Hu, X.S. Jiang, Q. Ye
    IHEP, People's Republic of China
  • G.H. Gong
    Tsinghua University, Beijing, People's Republic of China
  In this paper a new fast machine protection system is proposed. This system is designed for the injection Ι of C-ADS which fault reaction time requires less than 20us, and the one minute down time requires less than 7 times in a whole year. The system consist of one highly reliable control network based on a control board and some front IO sub-boards, and one nanosecond precision timing system using white rabbit protocol. The control board and front IO sub-board are redundant separately. The structure of the communication network is a combination structure of star and tree types which using the 2.5GHz optical fiber links the all nodes. This paper pioneered the use of nanosecond timing system based on the white rabbit protocol to determine the time and sequence of each system failure. Another advantage of the design is that it uses standard FMC and an easy extension structure which made the design is easy to use in a large accelerator.  
poster icon Poster MOPGF134 [0.820 MB]  
MOPGF138 Overview and Design Status of the Fast Beam Interlock System at ESS interface, operation, linac, electronics 1
  • A. Monera Martinez, R. Andersson, A. Nordt, M. Zaera-Sanz
    ESS, Lund, Sweden
  • C. Hilbes
    ZHAW, Winterthur, Switzerland
  The ESS, consisting of a pulsed proton linear accelerator, a rotating spallation target designed for an average beam power of up to 5 MW, and a suite of neutron instruments, requires a large variety of instrumentation, both for controlling as well as protecting the different hardware systems and the beam. The ESS beam power is unprecedented and an uncontrolled release could lead to serious damage of equipment installed along the tunnel and target station within only a few microseconds. Major failures of certain equipment will result in long repair times, because it is delicate and difficult to access and sometimes located in high radiation areas. To optimize the operational efficiency of the facility, accidents should be avoided and interruptions should be rare and limited to a short time. Hence, a sophisticated machine protection system is required. In order to stop efficiently the proton beam production in case of failures, a Fast Beam Interlock (FBI) system with a targeted reaction time of less than 5 microseconds and very high dependability is being designed. The design approach for this FPGA-based interlock system will be presented as well as the status on prototyping.  
poster icon Poster MOPGF138 [2.412 MB]  
MOPGF141 Upgrade of Abort Trigger System for SuperKEKB software, controls, timing, EPICS 1
  • S. Sasaki, A. Akiyama, M. Iwasaki, T. Naito, T.T. Nakamura
    KEK, Ibaraki, Japan
  The beam abort system was installed in KEKB in order to protect the accelerator equipment and the Belle detector, and for radiation safety, from high current beams. For SuperKEKB, the new abort trigger system was developed. It collects more than 130 beam abort request signals and issues the beam abort trigger signal to the abort kickers. The request signals are partially aggregated in local control rooms located along the SuperKEKB ring and finally aggregated in central control room. In order to increase the system reliability, the VME-based module and the O/E module was developed, and all the abort signals between the modules are transmitted as optical signals. The VME-based module aggregates input signals and input signals are OR and latched. The E/O module converts electrical signal from abort request source to optical signal. The system also has the timestamp function to keep track of the abort signal received time. The timestamps are expected to contribute to identify the cause of the beam abort. Based on feasibility tests with a prototype module, the new module design was improved and fixed. This paper describes the details of the new abort trigger system.  
poster icon Poster MOPGF141 [0.523 MB]  
MOPGF161 LANSCE Control System Upgrade Status and Challenges controls, hardware, EPICS, neutron 1
  • M. Pieck, D. Baros, E. Björklund, J.A. Faucett, J.G. Gioia, J.O. Hill, P.S. Marroquin, J.D. Paul, J.D. Sedillo, F.E. Shelley, H.A. Watkins
    LANL, Los Alamos, New Mexico, USA
  Funding: Work supported by Los Alamos National Laboratory for the U.S. Department of Energy under contract W-7405-ENG-36. LA-UR-15-27880
The Los Alamos Neutron Science Center (LANSCE) linear accelerator drives five user facilities: Isotope Production, Proton Radiography, Ultra-Cold Neutrons, Weapons Neutron Research, and Neutron Scattering. In 2011, we started an ambitious project to refurbish key elements of the LANSCE accelerator that have become obsolete or were near end-of-life. The control system went through an upgrade process that affected different areas of LANSCE. Many improvements have been made but funding challenges and LANSCE operational commitments have delayed project deliverables. In this paper, we will discuss our upgrade choices, what we have accomplished so far, what we have learned about upgrading the existing control system and what challenges we still face.
poster icon Poster MOPGF161 [1.069 MB]  
TUC3O04 Reusable Patient Safety System Framework for the Proton Therapy Centre at PSI GUI, EPICS, proton, interface 1
  • P. Fernandez Carmona, M. Eichin, M. Grossmann, A. Mayor, H.A. Regele
    PSI, Villigen, Switzerland
  • E. Johansen
    PSI, Villigen, Villigen, Switzerland
  A new gantry for cancer treatment is being installed at the Proton Therapy Centre in the Paul Scherrer Institut (PSI), where already two gantries and a fixed line operate. A protection system is required to ensure the safety of patients, requiring stricter redundancy, verification and quality assurance (QA) measures than other accelerators. It supervises the Therapy System, sensors, monitors and operator interface and can actuate magnets and beam blockers. We built a reusable framework to increase the maintainability of the system using the commercial IFC1210 VME controller, developed for other PSI facilities. It features a FPGA implementing all the safety logic and two processors, one dedicated to debugging and the other to integrating in the facility's EPICS environment. The framework permitted us to reduce the design and test time by an estimated 40% thanks to a modular approach. It will also allow a future renovation of other areas with minimum effort. Additionally it provides built-in diagnostics such as time measurement statistics, interlock analysis and internal visibility. The automation of several tasks reduces the burden of QA in an environment with tight time constraints.  
slides icon Slides TUC3O04 [10.385 MB]  
  • K. Ha, W.X. Cheng, L.R. Dalesio, J.H. De Long, Y. Hu, P. Ilinski, J. Mead, D. Padrazo, S. Seletskiy, O. Singh, R.M. Smith, Y. Tian
    BNL, Upton, Long Island, New York, USA
  • G. Shen
    FRIB, East Lansing, Michigan, USA
  Funding: Work supported by DOE contract No: DE-AC02-98CD10886
At National Synchrotron Light Source-II (NSLS-II), a field-programmable gate array (FPGA) based global active interlock system (AIS) has been commissioned and used for beam operations. The main propose of AIS is to protect insertion devices (ID) and vacuum chambers from the thermal damage of high density synchrotron radiation power. This report describes the status of AIS hardware, software architectures and operation experience.
slides icon Slides TUC3O05 [21.147 MB]  
WEC3O01 Trigger and RF Distribution Using White Rabbit timing, network, Ethernet, software 1
  • T. Włostowski, G. Daniluk, M.M. Lipinski, J. Serrano
    CERN, Geneva, Switzerland
  • F. Vaga
    University of Pavia, Pavia, Italy
  White Rabbit is an extension of Ethernet which allows remote synchronization of nodes with jitters of around 10ps. The technology can be used for a variety of purposes. This paper presents a fixed-latency trigger distribution system for the study of instabilities in the LHC. Fixed latency is achieved by precisely time-stamping incoming triggers, notifying other nodes via an Ethernet broadcast containing these time stamps and having these nodes produce pulses at well-defined time offsets. The same system is used to distribute the 89us LHC revolution tick. This paper also describes current efforts for distributing multiple RF signals over a WR network, using a Distributed DDS paradigm.  
slides icon Slides WEC3O01 [1.460 MB]  
WEPGF005 The New Modular Control System for Power Converters at CERN controls, interface, operation, high-voltage 1
  • M. Di Cosmo, B. Todd
    CERN, Geneva, Switzerland
  The CERN Accelerator Complex consists of several generations of particle accelerators, having around 5000 power converters supplying regulated current and voltage to normal and superconducting magnets. Today around 12 generations of legacy control system types are in operation in the accelerator complex, having significant impact on operability, support and flexibility for the converter controls electronics. Over the past years a new generation of modular controls called RegFGC3 has been developed by CERN's power conversion group. The goal is to provide a new standardised and cost effective control solution, supporting the largest number of converter topologies in a single platform. This will reduce the maintenance cost by decreasing the variety and diversity of control systems whilst simultaneously improving the operability of power converters. This paper describes Thyristor-based power converter controls as well as the on-going design and realization, focusing on functional requirements and first implementation.  
poster icon Poster WEPGF005 [1.126 MB]  
WEPGF029 High Level Software Structure for the European XFEL LLRF System LLRF, controls, electron, software 1
  • Ch. Schmidt, V. Ayvazyan, J. Branlard, L. Butkowski, O. Hensler, M. Killenberg, M. Omet, S. Pfeiffer, K.P. Przygoda, H. Schlarb
    DESY, Hamburg, Germany
  • W. Cichalewski, F. Makowski
    TUL-DMCS, Łódź, Poland
  • A. Piotrowski
    FastLogic Sp. z o.o., Łódź, Poland
  The Low level RF system for the European XFEL is controlling the accelerating RF fields in order to meet the specifications of the electron bunch parameters. A hardware platform based on the MicroTCA.4 standard has been chosen, to realize a reliable, remotely maintainable and high performing integrated system. Fast data transfer and processing is done by field programmable gate arrays (FPGA) within the crate, controlled by a CPU via PCIe communication. In addition to the MTCA system, the LLRF comprises external supporting modules also requiring control and monitoring software. In this paper the LLRF system high level software used in E-XFEL is presented. It is implemented as a semi-distributed architecture of front end server instances in combination with direct FPGA communication using fast optical links. Miscellaneous server tasks have to be executed, e.g. fast data acquisition and distribution, adaptation algorithms and updating controller parameters. Furthermore the inter-server data communication and integration within the control system environment as well as the interface to other subsystems are described.  
WEPGF074 FPGA Firmware Framework for MTCA.4 AMC Modules interface, hardware, framework, LLRF 1
  • Ł. Butkowski, T. Kozak, B.Y. Yang
    DESY, Hamburg, Germany
  • P. Prędki
    TUL-DMCS, Łódź, Poland
  • R. Rybaniec
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
  Many of the modules in specific hardware architectures use the same or similar communication interfaces and IO connectors. MicroTCA (MTCA.4) is one example of such a case. All boards: communicate with the central processing unit (CPU) over PCI Express (PCIe), send data to each other using Multi-Gigabit Transceivers (MGT), use the same backplane resources and have the same Zone3 IO or FPGA mezzanine card (FMC) connectors. All those interfaces are connected and implemented in Field Programmable Gate Array (FPGA) chips. It makes possible to separate the interface logic from the application logic. This structure allows to reuse already done firmware for one application and to create new application on the same module. Also, already developed code can be reused in new boards as a library. Proper structure allows the code to be reused and makes it easy to create new firmware. This paper will present structures of firmware framework and scripting ideas to speed up firmware development for MTCA.4 architecture. European XFEL control systems firmware, which uses the described framework, will be presented as example.  
poster icon Poster WEPGF074 [0.702 MB]  
WEPGF080 Encoder Interface for NSLS-II Beam Line Motion Scanning Applications interface, controls, status, hardware 1
  • R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski
    BNL, Upton, Long Island, New York, USA
  The variety of motion control applications on existing and future NSLS-II beam lines demand custom control electronics developed to meet specific needs and ease integration to existing systems. Thus an encoder interface was designed for a number of detection techniques that require fly-scan applications. This design fits in a 2U chassis and can handle up to 4 incremental quadrature encoders with a digital RS-422A interface and output frequencies up to 10 MHz. The logic, based on Xilinx Virtex-6 FPGA, processes signals from an encoder, associates it with accelerator timestamp and sends the data to a server using TCP/IP stack, with the server side running an EPICS IOC. Several filtering and compression techniques are also applied. The device then re-translates the interface signals for the motion controller, allowing the device to be installed between encoder and motion controller with no interference to the system. The hardware leverages the NSLS-II BPM Digital Front End (DFE) board with Virtex-6 FPGA and periphery. The design harmoniously complements the family of NSLS-II equipment sharing same mechanical and electrical platform.  
poster icon Poster WEPGF080 [4.670 MB]  
WEPGF081 Em# Platform: Towards a Hardware Interface Standardization Scheme controls, interface, hardware, electronics 1
  • O. Matilla, J.A. Avila-Abellan, M. Broseta, G. Cuní, D. Fernandez-Carreiras, A. Ruz, J. Salabert, X. Serra-Gallifa
    ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
  Low current measurements developments have been pointed out as strategic for ALBA synchrotron. From the first day of operation of the seven Beamlines currently in operation ALBA Em electrometer this has been successfully used. Today, the two new beamlines of Phase 2 that are being constructed and the new end stations have required specification changes in terms of increased accuracy, capability of synchronization, timestamping, management of large buffers and high performance closed-loop implementation. The scheme of full custom hardware design has been abandoned. ALBA Em# project approach has been based in the selection of industry standard interfaces: FMC boards design for custom needs, FMC carrier over PCIe using SPEC board from CERN under OHWR license, and Single Board Computer using PCIe to implement interfaces with the control system. This Paper describes the new design of the Electrometers at Alba, suited for the newer requirements, more flexible, performing and maintainable, which profits from the know-how acquired with previous versions and suits the new data acquisition paradigm emerged with the standardization of quick continuous scans and data acquisition.  
poster icon Poster WEPGF081 [0.230 MB]  
WEPGF084 New Digitisers for Position Sensitive 3He Proportional Counters detector, neutron, electronics, ion 1
  • P. Mutti, M. Plaz, E. Ruiz-Martinez, P. Van Esch
    ILL, Grenoble, France
  3He gas-filled detectors are a classical choice for the detection of thermal and cold neutrons. The incident neutrons are captured by the 3He producing a tritium and an hydrogen which are sharing the 765 keV of energy generated in the reaction. The classical geometry of a charge-division neutron detector consists of a cylindrical volume housing a resistive anode. Electrical signals are extracted at both ends of the tube and the information about the interaction point along the tube can be derived from the ratio of the collected charged at both ends. The classical analog approach for the charge readout consists of a shaping amplifier coupled with a peak sensing ADC. The development of a new digital front-end electronics based on 64 channels, 62.5 Msample/s and 12 bit digitisers, is reported on. Excellent results have been obtained in terms of position resolution and signal to noise ratio when adopting a continuous digital filtering and gaussian shaping.  
poster icon Poster WEPGF084 [8.285 MB]  
WEPGF089 CERN Open Hardware Experience: Upgrading the Diamond Fast Archiver hardware, network, interface, feedback 1
  • I.S. Uzun, M.G. Abbott
    DLS, Oxfordshire, United Kingdom
  Diamond Light Source developed and integrated the Fast Archiver into its Fast Orbit Feedback communication network in 2009. It enabled synchronous capture and archive of the entire position data in real-time from all Electron Beam Position Monitors (BPMs) and X-RAY BPMs . The FA Archiver solution has also been adopted by SOLEIL and ESRF. However, the obsolescence of the existing PCI Express based FPGA board from Xilinx and continuing interest from community forced us to look for a new hardware platform while keeping the back compatibility with the existing Linux kernel driver and application software. This paper reports our experience with using the PCIe SPEC board from CERN Open Hardware initiative as the new FA Archiver platform. Implementation of the SPEC-based FA Archiver has been successfully completed and recently deployed at ALBA in Spain.  
poster icon Poster WEPGF089 [0.576 MB]  
WEPGF124 Application Using Timing System of RAON Accelerator timing, controls, EPICS, Linux 1
  • S. Lee, H. Jang, C.W. Son
    IBS, Daejeon, Republic of Korea
  Funding: This work is supported by the Rare Isotope Science Project funded by Ministry of Science, ICT and Future Planning(MSIP) and National Research Foundation(NRF) of Korea(Project No. 2011-0032011).
RAON is a particle accelerator to research the interaction between the nucleus forming a rare isotope as Korean heavy-ion accelerator. RAON accelerator consists of a number of facilities and equipments as a large-scaled experimental device operating under the distributed environment. For synchronization control between these experimental devices, timing system of the RAON uses the VME-based EVG/EVR system. In order to test the high-speed performance of the control logic with the minimized event signal delay, it is planned to establish the step motor controller testbed applying the FPGA chip. The testbed controller will be configured with Zynq 7000 series of Xilinx FPGA chip. Zynq as SoC (System on Chip) is divided into PS (Processing System) with PL (Programmable Logic). PS with the dual-core ARM cpu is performing the high-level control logic at run-time on linux operating system. PL with the low-level FPGA I/O signal interfaces with the step motor controller with the event signal received from timing system. This paper describes the content and performance evaluation obtained from the step motor control through the various synchronized event signal received from the timing system.
poster icon Poster WEPGF124 [1.690 MB]  
THHA2I01 Developing Distributed Hard-Real Time Software Systems Using FPGAs and Soft Cores real-time, controls, software, distributed 1
  • T. Włostowski, J. Serrano
    CERN, Geneva, Switzerland
  • F. Vaga
    University of Pavia, Pavia, Italy
  Hard real-time systems guarantee by design that no deadline is ever missed. In a distributed environment such as particle accelerators, there is often the extra requirement of having diverse real-time systems synchronize to each other. Implementations on top of general-purpose multi-tasking operating systems such as Linux generally suffer from lack of full control of the platform. On the other hand, solutions based on logic inside FPGAs can result in long development cycles. A mid-way approach is presented which allows fast software development yet guarantees full control of the timing of the execution. The solution involves using soft cores inside FPGAs, running single tasks without interrupts and without an operating system underneath. Two CERN developments are presented, both based on a unique free and open source HDL core comprising a parameterizable number of CPUs, logic to synchronize them and message queues to communicate with the local host and with remote systems. This development environment is being offered as a service to fill the gap between Linux-based solutions and full-hardware implementations.  
slides icon Slides THHA2I01 [2.525 MB]  
THHA2O02 The LASNCE FPGA Embedded Signal Processing Framework framework, software, hardware, interface 1
  • J.O. Hill
    LANL, Los Alamos, New Mexico, USA
  Funding: Work supported by US Department of Energy under contract DE-AC52-06NA25396.
During the replacement of some LANSCE LINAC instrumentation systems a common architecture for timing system synchronized embedded signal processing systems was developed. The design follows trends of increasing levels of electronics system integration; a single commercial-off-the-shelf (COTS) board assumes the roles of analog-to-digital conversion and advanced signal processing while also providing the LAN attached EPICS IOC functionality. These systems are based on agile FPGA-based COTS VITA VPX boards with an VITA FMC mezzanine site. The signal processing is primarily developed at a high level specifying numeric algorithms in software source code to be integrated together with COTS signal processing intellectual property components for synthesis of hardware implementations. This paper will discuss the requirements, the decision point selecting the VPX together with the FMC industry standards, the benefits along with costs of system integrating multi-vendor COTS components, the design of some of the signal processing algorithms, and the benefits along with costs of embedding the EPICS IOC within an FPGA.
slides icon Slides THHA2O02 [2.108 MB]  
THHA2O03 Message Signalled Interrupts in Mixed-Master Control controls, operation, target, network 1
  • W.W. Terpstra, M. Kreider
    GSI, Darmstadt, Germany
  Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.  
slides icon Slides THHA2O03 [0.758 MB]  
THHB2O02 A Modular Approach to Acquisition Systems for Future CERN Beam Instrumentation Developments radiation, instrumentation, timing, interface 1
  • A. Boccardi, M. Barros Marin, T.E. Levens, W. Viganò, C. Zamantzas
    CERN, Geneva, Switzerland
  This paper will present the new modular architecture adopted as a baseline by the CERN Beam Instrumentation Group for its future acquisition system developments. The main blocks of this architecture are: radiation tolerant digital front-ends; a latency deterministic multi gigabit optical link; a high pin count FMC carrier used as a VME-based back-end for data concentration and processing. Details will be given on the design criteria for each of these modules as well as examples of their use in systems currently being developed at CERN.  
slides icon Slides THHB2O02 [2.051 MB]